The present invention relates to an active-matrix-type image display having a plurality of video signal lines installed therein and its driving method.
In an active-matrix-type liquid crystal display having an integrated driving circuit, it is necessary to provide driving circuits, such as a source driver and a gate driver on an insulating substrate made of glass, crystal, etc., as integral parts with a display section, and the driving circuits are normally formed by polysilicon thin-film MOS transistors (hereinafter, referred to as polysilicon TFTs).
However, the driving circuit using polysilicon TFTs has the disadvantage of a very slow operation speed as compared with a driving circuit using monocrystal silicon. In particular, in the case where a large-screen, high-capacity displaying operation is carried out in the source driver for driving the source bus line in the display section, since sift registers constituting the source driver fail to provide a sufficient operation speed, various methods for carrying out a driving operation without exceeding the speed of the shift registers constituted by polysilicon TFTs have been considered.
FIG. 18 shows an active-matrix-type liquid crystal display of a driving-circuit-build-in type using two systems of shift registers, which is one example of a method for decreasing the operation speed required for the sift registers. Referring to FIG. 18, an explanation will be given of a construction of a conventional active-matrix-type liquid crystal display of the driving-circuit-built-in type.
As illustrated in the Figure, in this liquid crystal display, source bus lines s1 through sN and gate bus lines g1 through gM are wired in warp and woof on an insulating substrate 101 so that a display section 102 is formed. On the substrate 101 on which the display section 102 is formed, a source driver 103 for driving the source bus lines s1 through sN is formed at one end of the source bus lines s1 through sN and a gate driver 104 for driving the gate bus lines g1 through gM is formed at one end of the gate bus lines g1 through gM.
In the display section 102, each of portions, surrounded by the source bus lines sn (1xe2x89xa6nxe2x89xa6N) and the gate bus lines gm (1xe2x89xa6mxe2x89xa6M), forms a pixel 120 which is one unit of display. Referring to FIG. 2 that is an explanatory drawing of one Embodiment of the present invention, an explanation will be given of the pixel 120. The pixel 120 is constituted by a thin-film transistor 20a functioning as a switching element that is formed at an intersecting point between each source bus line Sn and each gate bus line Gm, a pixel electrode 20b to which video signal electric potentials D1, D2, etc. provided from the source bus lines Sn are applied so as to drive a liquid crystal capacitor and a charge-holding capacitor 20c installed in parallel with the pixel electrode 20b. 
As illustrated in FIG. 18, the source driver 103 is constituted by two video signal lines 131a and 131b for inputting video signals VideoI and VideoII to the source bus lines s1 through sN, a sampling circuit constituted by an analog switch 132 formed between the video signal lines 131axc2x7131b and the respective source bus lines s1 through sN, and two systems of shift registers SRa and SRb for controlling the operation of the analog switch 132.
The odd numbered source bus lines s1 through sNxe2x88x921 are connected to the video signal line 131a so that the video signal VideoI is applied thereto. The even numbered source bus lines s2 through sN are connected to the video signal lines 131b so that the video signal VideoII is applied thereto. The analog switch 132 is used for sampling the video signals VideoI and VideoII from the video signal lines 131a and 131b. 
The two systems of shift registers SRa and SRb are alternately connected to the source bus lines s1 through sN so that the shift register SRa controls the operation (opening and shutting) of the analog switch 132 corresponding to the odd numbered source bus lines s1 through snxe2x88x921, while the shift register SRb controls the operation of the analog switch 132 corresponding to the even numbered source bus lines s2 through sN.
The respective parts constituting the source driver 103 are formed on the same substrate 101 by using polysilicon thin-films, etc.
FIG. 19 shows a timing chart upon driving the source driver 103 shown in FIG. 18. Referring to FIGS. 18 and 19, an explanation will be given of the driving operation of the source driver 103.
The activation of the two systems of shift registers SRa and SRb is controlled by a shift start signal SP shown in FIG. 19. The shift register SRa is controlled by shift clock signals xcfx86Axc2x7/xcfx86A and the shift register SRb is controlled by shift clock signals xcfx86Bxc2x7/xcfx86B. Signals whose phases are shifted from each other by a xc2xc period (a sampling period t0 corresponding to a value obtained by dividing the effective horizontal scanning period by the number of the effective source bus lines) are used as the shift clock signal xcfx86A and the shift clock signal xcfx86B. Accordingly, these shift clock signals xcfx86Axc2x7/xcfx86Axc2x7xcfx86Bxc2x7/xcfx86B allow the two shift registers SRa and SRb to output waveforms whose phases are respectively shifted from each other by the sampling period t0 to the analog switch 132 successively.
The video signals VideoI and VideoII, which are formed by outputting for the period 2t0 video signal electric potentials D1, D2, . . . , etc. that have been obtained by sampling an original video signal Video with its phase respectively shifted by period t0, are inputted to the two video signal lines 131a and 131b respectively. The method for forming the video signals VideoI and VideoII will be described later in detail.
In this case, the two analog switches 132, each of which is controlled by one output of each of the registers SRa and SRb, are connected to the respectively different video signal lines 131a and 131b, and successively sample the video signal electric potentials D1, D2, . . . , etc. having mutually different phases, as in the cases of video signals VideoI and VideoII shown in FIG. 19. The analog switch 132 is allowed to conduct during a period in which the output of each of the shift registers SRa and SRb goes high, and one output of each of the shift registers SRa and SRb allows one of the analog switches 132 to conduct for period 4t0.
During the period in which the analog switch 132 is allowed to conduct, the video signal VideoI or VideoII is sampled so that the source bus lines s1 through sN are successively driven. Since the analog switch 132 in question is connected to the same video signal lines 131a and 131b that are connected to the analog switch 132 connected to the source bus lines s1 through sN located two lines before, it is allowed to conduct with an overlapping period of 2t0 with the analog switch 132 connected to the source bus lines s1 through sN located two lines before. As a result, the video signals VideoI and VideoII are sampled during the last period 2t0 (the period in which no overlapping is made with the source bus lines s1 through sN located two lines before).
By carrying out the driving operation as described above, the video signal electric potentials D1, D2 . . . , etc., which are mutually shifted by the sampling period t0, are applied to the source bus lines s1 through sN.
Here, FIG. 20 shows one example of a video-signal forming circuit for converting an original video signal Video into two kinds of video signals VideoI and VideoII. Referring to FIG. 20, an explanation will be given of the construction of the video-signal forming circuit.
As illustrated in the Figure, an A/D conversion circuit, to which an original video signal Video is inputted and which. A/D converts the inputted original video signal Video as well as sampling it for the sampling period t0, is provided, and a gamma xcex3 correction circuit 142 is connected to the output side thereof. The gamma correction circuit 142 is a circuit which carries out a correcting operation by non-linearly converting the output from the A/D conversion circuit 141 so that a correct brightness is reproduced with respect to the original video signal Video in a liquid crystal display.
Two systems of data latch circuits 143b and 143c for latching the output signal of the gamma correction circuit 142 are connected to the output side of the gamma correction circuit 142. A buffer amplifier circuit 145b is connected to the output side of the data latch circuit 143b through a D/A conversion circuit 144b, and a buffer amplifier circuit 145c is connected to the output side of the data latch circuit 143c through a D/A conversion circuit 144c. Moreover, a gain-offset correction circuit 146, which corrects the level difference between two systems of video signals VideoI and VideoII based upon video signals VideoI and VideoII that are the outputs of the buffer amplifiers 145b and 145c, is provided.
FIG. 21 shows a timing chart which indicates the operation of the video-signal forming circuit. Referring to FIG. 21, an explanation will be given of the operation of the video signal forming circuit.
First, an original video signal Video is inputted to the A/D conversion circuit 141, and the A/D conversion circuit 141 A/D converts the inputted original video signal Video, as well as sampling it during the sampling period t0 as shown in FIG. 21, thereby outputting the video signal electric potentials D1, D2, . . . , etc. The output from the A/D conversion circuit 141 is inputted to the gamma correction circuit 142 where it is subjected to a gamma correction.
Next, the output of the gamma correction circuit 141 is inputted to the two systems of data latch circuits 143b and 143c. In the two systems of data latch circuits 143b and 143c, the video signal electric potentials D1, D2 . . . , etc. are latched with a period two times the sampling period t0 by clock signals CKb and CKc whose phases are mutually shifted by the sampling period t0. At this time, as shown in the Figure, the odd-numbered video signal electric potentials D1, D3, . . . , etc. are latched into the data latch circuit 143b, and as shown in the Figure, the even-numbered video signal electric potentials D2, D4, . . . , etc. are latched into the data latch circuit 143c. 
The outputs of the two systems of data latch circuits 143b and 143c are inputted to the corresponding D/A conversion circuits 144b and 144c. The D/A conversion circuits 144b and 144c are driven by the clock signals CKd and CKe, with the result that the video signal electric potentials D1, D2, . . . , etc. are inputted to the respective buffer amplifier circuits 145b and 145c in timing whose phases are mutually shifted by the sampling period t0.
In this manner, the above-mentioned two kinds of video signals VideoI and VideoII are obtained.
The above-mentioned conventional active-matrix-type liquid crystal display of the driving-circuit built-in type has a structure in which the two shift registers SRa and SRb and the two video signal lines 131a and 131b are provided (see FIG. 18); and in this case, in the video-signal forming circuit provided on the external portion of the substrate, the data latch circuits 143b and 143c, the D/A conversion circuits 144b and 144c and the buffer amplifier circuits 145b and 145c, the numbers of which are equal to a number by which the video signal is divided (in this case, xe2x80x9ctwoxe2x80x9d), need to be installed in order to produce the two systems of video signals VideoI and VideoII (see FIG. 20).
Here, in this liquid crystal display, in the case when an image merely requiring half of the scanning frequency of the present condition is displayed, this is easily achieved by using a method in which the frequency of each of the shift clock signals xcfx86Axc2x7/xcfx86Axc2x7xcfx86Bxc2x7/xcfx86B to be inputted to the shift registers SRa and SRb is reduced to half.
However, such a method for reducing the frequency of each of the shift clock signals xcfx86Axc2x7/xcfx86Axc2x7xcfx86Bxc2x7/xcfx86B to half fails to provide a frequency suitable for the construction of external circuits such as the video-signal forming circuit, resulting in the following problems.
Since merely requiring half of the scanning frequency of the present condition means that it is not necessary to divide the video signal into two, it becomes possible to design a construction in which the aforementioned video-signal forming circuit, installed in the external portion of the substrate, merely requires one group of the data latch circuit, D/A conversion circuit and buffer amplifier circuit, or one buffer amplifier, so that the cost reduction can be achieved by miniaturizing the circuit scale; however, the above-mentioned method fails to cut costs because the number of systems for the video signal is not reduced.
Further, when the video signal is divided, buffer amplifiers that deal with the corresponding video signals are required, and the increased number of buffer amplifiers causes the disadvantage that stripes resulting from irregularities in offsets of the amplifiers become conspicuous; therefore, it is preferable to avoid unnecessary division of the video signal.
Therefore, the external circuits, such as the video-signal forming circuit, should be appropriately designed so as to fit the scanning frequency.
However, in contrast, in the case when the circuit construction suitable for the scanning frequency is provided, although the resulting cost reduction is achieved, the substrate for constituting the active-matrix-type liquid crystal display has to be reconstructed in its design, thereby cancelling the cost reduction effects that have been achieved.
The present invention has been devised to solve the above-mentioned problems, and its objective is to provide a driving method for an image display having the following advantages and an image display using such a driving method. In other words, even in the case where it is applied to another system using a different scanning frequency, such as in the case where, for example, a liquid crystal display, which is designed based on the XGA (extended graphics array) standard and has 1024xc3x97768 pixels, is sharedly used as a TV-image-receiving liquid crystal display for displaying a video signal of the NTSC (National Television System Committee) system, the driving method is capable of providing a shared use of a substrate and reducing the costs, while allowing the construction of the external circuit to become suitable for the different scanning frequency.
In order to achieve the above-mentioned objective, the driving method for the active-matrix-type image display of the present invention is a driving method which is provided with: a plurality of gate bus lines and a plurality of source bus lines, which are mutually orthogonalized on a substrate, and a source driving circuit for driving the source bus lines, the source driving circuit being provided with switching means formed in the respective source bus lines and opening and closing control sections for controlling the opening and closing of the respective switching means, with the respective switching means being connected to the plural video signal lines one by one in succession. The driving method for the active-matrix-type image display is characterized in that in the case when the number of divisions of the video signal is reduced in response to the scanning frequency of an original video signal, the plural video signal lines are divided into groups the number of which corresponds to the reduced number of divisions so that the same video signal is inputted to the video signal lines that belong to the same group.
In order to achieve the above-mentioned objective, the driving method for the active-matrix-type image display of the present invention is a driving method which is provided with: a plurality of gate bus lines and a plurality of source bus lines, which are mutually orthogonalized on a substrate, and a source driving circuit for driving the source bus lines, the source driving circuit being provided with a switching circuit connected to a plurality of video signal lines for transmitting a video signal. The driving method for the active-matrix-type image display is characterized in that the video signal is divided into a number corresponding to the scanning frequency of the video signal, and in the case when the number of divisions of the video signal is fewer than the number of the video signal lines, the plural video signal lines are grouped so as to form groups the number of which is equal to the number of divisions so that the same video signal is inputted to the video signal lines that belong to the same group.
With the above-mentioned driving methods, even in the case when an original video signal, which has a scanning frequency that is lower than the scanning frequency initially set at the time of the substrate design, is displayed, the number of divisions of the video signal is properly set so as to fit the low scanning frequency. In other words, the shared use of the substrate is available, the cost reduction is achieved by optimizing the external circuit construction (scale), such as that of the video-signal forming circuit, so as to fit the low scanning frequency as described in the section of the prior art, and the disadvantage of stripes, which appears due to offset irregularities of the amplifiers caused by an increase in the number of the buffer amplifier circuits, can be suppressed. As a result, it becomes possible to achieve a great reduction in costs in an active-matrix-type image display.
In the above-mentioned driving methods, if the opening and closing control sections in the source driving circuit are constituted by shift registers forming a plurality of systems, the number of divisions of a shift clock signal corresponding to the number of the systems of the shift registers may also be reduced in accordance with the number of divisions of the video signal lines so that the same driving operation can be carried out by inputting the same shift lock signal to different shift registers.
As compared with a construction for driving the shift registers individually without reducing the number of divisions of a shift clock, this arrangement makes it possible to reduce the external circuit scale, thereby further miniaturizing the external circuit scale as compared with the above-mentioned driving methods.
Moreover, in the above-mentioned driving methods, the number of divisions of a shift start signal corresponding to the number of the systems of the shift registers may also be reduced in accordance with the number of divisions of the video signal lines so that the same shift lock signal may be inputted to different shift registers.
In such a construction where the shift start signal is also divided in accordance with the number of systems of the shift registers, as compared with a construction for supplying shift start signals to individual shift registers without reducing the number of divisions of a shift start signal, it becomes possible to reduce the external circuit scale, thereby further miniaturizing the external circuit scale as compared with the above-mentioned driving methods.
Furthermore, in the above-mentioned driving methods, if the opening and closing control sections in the source driving circuit are constituted by decoder circuits forming a plurality of systems, the number of divisions of signals to be supplied to the respective decoder circuits may also be reduced in accordance with the number of divisions of the video signal lines so that the same driving operation can be carried out by inputting the same signal to different decoder circuits.
In the case when selection of the source bus lines is carried out by using decoder circuits, as compared with a construction for driving the decoder circuits individually without reducing the number of divisions of signals to be supplied to the respective decoder circuits, the driving operation as described above makes it possible to reduce the external circuit scale, thereby further miniaturizing the external circuit scale as compared with the above-mentioned driving methods.
In order to achieve the above-mentioned objective, the active-matrix-type image display of the present invention is. an image display which is provided with: a plurality of gate bus lines and a plurality of source bus lines, which are mutually orthogonalized on a substrate, and a source driving circuit for driving the source bus lines, the source driving circuit being provided with switching means formed in the respective source bus lines and opening and closing control sections for controlling the opening and closing of the respective switching means, with the respective switching means being connected to the plural video signal lines one by one in succession. The active-matrix-type image display is characterized in that it is further provided with a first switching means for making switchovers between a state in which the plural video signal lines are disconnected from each other so that discrete video signals are transmitted and a state in which predetermined video signal lines, selected among the plural video signal lines, are connected to each other so that the same video signal is transmitted in the predetermined video signal lines.
In order to achieve the above-mentioned objective, the active-matrix-type image display of the present invention is an image display which is provided with: a plurality of gate bus lines and a plurality of source bus lines, which are mutually orthogonalized on a substrate, and a source driving circuit for driving the source bus lines, the source driving circuit being provided with a switching circuit connected to a plurality of video signal lines for transmitting a video signal. The active-matrix-type image display is characterized in that it is further provided with a first switching means for making switchovers between a state in which the video signal lines are mutually disconnected so as to transmit discrete video signals in accordance with the scanning frequency of a video signal and a state in which predetermined video signal lines, selected among the plural video signal lines, are connected so as to transmit the same video signal in the predetermined video signal lines.
With the above-mentioned arrangement, since the first switching means provides the state in which the predetermined video signal lines are mutually connected when occasion calls, the active-matrix-type image display can be used for displaying an original video signal having a scanning frequency lower than the scanning frequency as designed a and when the driving method of the present invention is carried out, it becomes possible to reduce the number of input signals to the source driving circuit. Therefore, reliability is improved in making connection between the substrate and an external device. Consequently, it becomes possible to provide an active-matrix-type image display in which the driving method of the present invention is preferably adopted.
In the active-matrix-type image display of the present invention, it is preferable to further provide an arrangement in which: the opening and closing control section of the source driving circuit is constituted by shift registers forming a plurality of systems, and a second switching means, which makes switchovers between a state in which a plurality of shift clock signal lines, which supply shift clock signals to the shift registers, are mutually disconnected so as to transmit discrete shift clock signals and a state in which predetermined shift clock signal lines, selected among the plural shift clock signal lines, are connected so as to transmit the same shift clock signal in the predetermined shift clock signal lines, is installed.
With the above-mentioned arrangement, since the second switching means provides the state in which the predetermined shift clock signal lines are mutually connected when occasion calls, the active-matrix-type image display can be used for displaying an original video signal having a scanning frequency lower than the scanning frequency as designed, and when the driving method of the present invention is carried out, it becomes possible to reduce the number of input signals to the source driving circuit. Therefore, reliability is improved in making connection between the substrate and an external device. Consequently, it becomes possible to provide an active-matrix-type image display in which the driving method of the present invention is preferably adopted.
In the active-matrix-type image display of the present invention, it is preferable to further provide a third switching means which makes switchovers between a state in which a plurality of shift start signal lines, which supply shift start signals to the shift registers, are mutually disconnected so as to transmit discrete shift start signals and a state in which predetermined shift start signal lines, selected among the plural shift start signal lines, are connected so as to transmit the same shift start signal in the predetermined shift start signal lines.
With the above-mentioned arrangement, since the third switching means provides the state in which the predetermined shift start signal lines are mutually connected when occasion calls, the active-matrix-type image display can be used for displaying an original video signal having a scanning frequency lower than the scanning frequency as designed, and when the driving method of the present invention is carried out, it becomes possible to reduce the number of input signals to the source driving circuit. Therefore, reliability is improved in making connection between the substrate and an external device. Consequently, it becomes possible to provide an active-matrix-type image display in which the driving method of the present invention is preferably adopted.
In the active-matrix-type image display of the present invention, it is preferable to further provide an arrangement in which: the opening and closing control section of the source driving circuit is constituted by decoder circuits forming a plurality of systems, and a fourth switching means, which makes switchovers between a state in which a plurality of signal lines, which supply signals to the decoder circuits, are mutually disconnected so as to transmit discrete signals and a state in which predetermined signal lines, selected among the plural of signal lines, are connected so as to transmit the same signal in the predetermined signal lines, is installed.
With the above-mentioned arrangement, since the fourth switching means provides the state in which the predetermined signal lines are mutually connected when occasion calls, the active-matrix-type image display can be used for displaying an original video signal having a scanning frequency lower than the scanning frequency as designed, and when the driving method of the present invention is carried out, it becomes possible to reduce the number of input signals to the source driving circuit. Therefore, reliability is improved in making connection between the substrate and an external device. Consequently, it becomes possible to provide an active-matrix-type image display in which the driving method of the present invention is preferably adopted.
The active-matrix-type image display of the present invention is characterized in that the circuit constituting the above-mentioned switching means (the first through fourth switching means), the source driving circuit and the gate driving circuit for driving the gate bus lines are formed on the same substrate that is provided with the source bus lines and gate bus lines.
With the above-mentioned arrangement, as compared with an arrangement in which the circuit constituting switching means, the source driving circuit and the gate driving circuit for driving the gate bus lines are formed outside the substrate that is provided with the source bus lines and the gate bus lines, it is possible to reduce the manufacturing costs. Consequently, it becomes possible to reduce the price of an active-matrix-type image display.
Other objects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the drawings in which: